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Verification Engineer
Sin especificarTiempo completoQA & Test AutomationAutomotive Technology
Join a unit-level verification team developing verification environments for AI and deep-learning hardware accelerators used in autonomous-vehicle computing systems.
Responsabilidades
- Define, implement, and enhance UVM-based verification environments
- Write and debug tests combining UVM methodology with software code
- Create and analyze multiple types of coverage measures
- Collaborate with designers, architects, and software developers across engineering teams
- Integrate industry-standard protocols and third-party verification IPs
Requisitos
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- At least 4 years of experience with verification environments, tests, and testbench development
- SystemVerilog skills, preferably with OVM or UVM
- Embedded software experience and C/C++ skills
- Experience defining test plans and performing coverage-driven verification
- Experience with third-party IP integration testing
- Ability to debug waveforms using EDA tools and independently identify bug root causes
Se valora
- Perl or Python scripting skills
- Knowledge of AXI, OCP, or APB protocols