Q
Senior Pre-Silicon Verification Engineer
PresencialTiempo completoQA & Test AutomationSemiconductor Manufacturing
Join an engineering team developing verification environments for advanced high-speed ASIC products. The role focuses on block- and cluster-level verification using SystemVerilog UVM and formal verification methods.
Responsabilidades
- Develop block- and cluster-level test environments
- Create test plans and define coverage
- Work closely with design and architecture teams
- Use SystemVerilog UVM and formal verification environments
- Contribute to verification of advanced high-speed products
Requisitos
- Bachelor’s degree in electrical engineering, computer science, science, engineering, or a related field; equivalent master’s or doctoral qualifications may also apply
- At least 4 years of ASIC design, verification, validation, integration, or related experience; 5 years of pre-silicon verification experience is preferred
- Experience with SystemVerilog UVM
- Very good English communication skills
- Strong writing and presentation skills
Se valora
- Formal verification experience
- Experience with networking products