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Functional Verification Engineer – Applied ML
PresencialTiempo completoQA & Test AutomationSemiconductorEnterprise Software
Develop AI-assisted pre-silicon verification solutions for semiconductor design, combining formal verification, simulation, UVM methodologies, machine learning, and EDA tools.
Responsabilidades
- Apply machine learning techniques to streamline formal verification and UVM-based pre-silicon verification
- Develop agentic AI solutions using large language models and current machine learning technologies
- Use AI-enhanced EDA tools to improve chip design and verification workflows
- Work with customers to understand requirements and deliver practical verification strategies
- Collaborate with machine learning and software engineering teams to validate correctness, efficiency, and quality
- Track advances in AI-powered hardware verification and contribute to internal knowledge sharing
Requisitos
- Bachelor’s degree with at least 4 years of experience, master’s degree with at least 2 years of experience, or a newly completed PhD
- More than 3 years of experience with at least one pre-silicon ASIC verification methodology, such as formal verification, SystemVerilog/UVM, or OVM
- Advanced debugging skills using waveform viewers and simulation analysis tools
- Hands-on experience with industry-standard EDA tools such as Jasper, Xcelium, or IMC
- Strong programming skills in Verilog, SystemVerilog, and Python
- Strong communication and collaboration skills
- Self-motivated approach to problem solving, continuous learning, and innovation
Se valora
- Exposure to LLMs, retrieval-augmented generation, reinforcement learning, or agentic frameworks
- Experience applying machine learning to hardware verification
Beneficios
- Opportunity to work on advanced AI and semiconductor design technology
- Employee well-being and career development programs
- Learning and development opportunities
- Collaborative, cross-functional team environment