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Staff Physical Design Engineer
PresencialTiempo completoHardware EngineeringSemiconductor Manufacturing
Join an Israel-based semiconductor R&D team developing complex connectivity chips for large-scale AI infrastructure. Own top-level SoC physical design from implementation through tape-out and signoff.
Responsabilidades
- Execute top-level SoC physical design and drive full-chip convergence.
- Perform floorplanning, place and route, clock-tree synthesis, power and clock distribution, power-integrity analysis, and timing and physical signoff.
- Drive tape-out GDS delivery against timing, LVS, EMIR, DRC, and other signoff criteria.
- Collaborate with architecture, design, DFT, product, and package teams to optimize power, performance, and area.
- Support architecture feasibility studies and optimize implementation runs for quality of results.
- Resolve signal-integrity, thermal, and power challenges in high-speed connectivity silicon.
- Develop bump-map-to-ballout designs with the package team while addressing signal-integrity requirements.
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering.
- At least 5 years of hands-on chip top physical design or backend experience at a semiconductor company.
- Experience with advanced process technologies at 5nm, 3nm, or below.
- Experience delivering complex block- or chip-level projects.
- Expertise in RTL-to-GDS flows, including place and route, static timing analysis, physical verification, formal verification, low-power implementation, and EMIR analysis.
- Proficiency with Synopsys Fusion Compiler or ICC2, or Cadence Innovus.
- Experience with macro or subsystem designs and full-chip integration.
- Strong communication and problem-solving skills.
Se valora
- Deep understanding of electromigration and IR-drop analysis.
- Experience integrating DFT into physical design flows.
- Background in high-speed interfaces or data center protocols.