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Senior Static Timing Analysis Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductors
Join a leading semiconductor company to perform advanced static timing analysis for high-speed networking silicon. Responsible for full timing closure from pre-layout to signoff, collaborating with physical design, RTL, and DFT teams. Requires 5+ years hands-on STA experience and AI tools orientation.
Responsabilidades
- Perform advanced static timing analysis (STA) for high-speed I/O (HSIO) at chiplet and full-chip (FC) level.
- Run Primetime, review and debug timing paths, understand constraints, generate SDC, and produce timing ECOs.
- Identify convergence risks and collaborate with physical design, RTL, and DFT teams to ensure timing convergence.
- Own full timing closure and quality approval from pre-layout STA model through signoff.
- Utilize AI for timing optimization and data analysis.
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering.
- 5+ years of hands-on STA experience.
- Experience with Primetime and signoff methodologies.
- Strong teamwork and collaboration skills.
- AI tools orientation or willingness to learn.
Se valora
- Experience with agentic frameworks.
- AI prompting experience.
- Linux environment experience.
- Scripting in TCL, Python, or shell.
- Data collection and analysis experience.