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Senior SoC Power Architect
Sin especificarTiempo completoHardware EngineeringComputer Hardware Manufacturing
Lead power optimization architecture for next-generation ASIC, DPU, and networking products, balancing power, performance, area, and design execution across silicon development.
Responsabilidades
- Develop architectures, algorithms, models, and methodologies to improve power consumption in DPU and NIC products
- Research power optimization techniques and power modeling approaches
- Define power-aware architecture requirements and implementation strategies
- Balance power, performance, area, and design execution considerations
- Work with board, package, and physical-design teams on power delivery, di/dt, thermal, and signal-integrity constraints
- Collaborate with software, ASIC design, verification, and platform teams to drive end-to-end power improvements
Requisitos
- Bachelor’s or master’s degree in electrical engineering or a related field
- At least 5 years of experience in ASIC design, microarchitecture, architecture, or performance
- Strong electrical engineering fundamentals, including digital design, front-end and back-end practices, power analysis, and characterization
- Strong analytical and problem-solving abilities
- Ability to lead complex activities across multiple disciplines and teams
- Effective teamwork and interpersonal communication skills
Se valora
- Experience as a hardware architect on high-end ASICs
- Computer architecture background focused on power management, optimization, characterization, or modeling
- Track record of power or performance improvements on silicon products
- Knowledge of physical-design back-end practices and their interaction with power architecture