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Senior SoC Design Verification Engineer
PresencialTiempo completoHardware EngineeringCloud Computing
Join our custom silicon team to verify digital logic designs for high-performance SoCs. Develop verification strategies, build UVM environments, and ensure functional correctness through coverage-driven methodology.
Responsabilidades
- Plan verification of digital design blocks by understanding specifications and identifying critical scenarios.
- Develop and enhance constrained-random verification environments using SystemVerilog and UVM.
- Identify and implement comprehensive coverage measures to expose corner-case bugs.
- Debug and collaborate with design engineers to deliver functionally correct designs.
- Drive verification closure and track progress toward tape-out.
Requisitos
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8+ years of experience with verification components and methodologies.
- Proficiency in verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Se valora
- Master's or PhD in Electrical Engineering or related field.
- Experience with verification techniques and full life cycle.
- Experience with performance verification of ASICs.
- Experience with ASIC standard interfaces and memory system architecture.
- Experience in multiple SoC cycles.