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Senior RTL Design Engineer – SOC Clocks
PresencialTiempo completoHardware EngineeringElectronics Manufacturing
Lead the implementation of SOC clocking and reset logic for next-generation networking chips, partnering with architecture, verification, physical design, DFT, CAD, and software teams through tape-out and silicon bring-up.
Responsabilidades
- Lead SOC clocking development from specification through tape-out and bring-up
- Translate clock and reset architectures into verifiable RTL designs
- Write and review synthesizable Verilog/SystemVerilog for clock generation, distribution, muxing, division, gating, switching, and reset synchronization
- Mentor RTL engineers, review designs, establish coding standards, and distribute work
- Collaborate with physical design on clock trees, SDC and timing constraints, partitioning, floorplan feedback, synthesis, and timing convergence
- Partner with design verification on test plans, functional and gate-level debugging, and coverage closure
- Support software and firmware teams with clock programming, DVFS, and clock-shutdown flows
- Represent clocking implementation in cross-functional design reviews
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering
- At least 8 years of relevant RTL or logic design experience
- Experience taking multiple chips through tape-out
- Technical leadership experience, including mentoring and cross-functional coordination
- Expertise in synthesizable Verilog/SystemVerilog RTL
- Deep knowledge of clock gating, clock muxing, dividers, glitchless switching, reset synchronization, and clock domain crossing
- Experience with lint, CDC/RDC, formal verification, synthesis, and static timing analysis
- Experience taking designs from architecture and micro-architecture through verification, physical implementation, and silicon bring-up
Se valora
- SOC-level clocking or reset logic experience on a taped-out chip
- PLL or clock generator integration experience
- Clock tree constraint development with backend teams
- Experience with networking, interconnect, or fabric designs
- Low-power design experience, including DVFS, power domains, or UPF
- Automation experience for RTL integration, chip assembly, or design-quality flows