Senior Physical Design Engineer
Own end-to-end physical design for next-generation SoCs, from definition and constraints through RTL collaboration, implementation, verification, signoff, and tape-out.
Responsabilidades
- Own physical design blocks from RTL through GDS and final tape-out.
- Explore floorplans and collaborate with front-end design and architecture teams.
- Perform synthesis exploration and final synthesis, including SDC definition, scan insertion, lint, LEC, UPF/low-power checks, and SpyGlass verification.
- Execute place-and-route through final layout and signoff, optimizing power, performance, and area.
- Perform static timing analysis and manage block- and top-level constraints with subsystem and full-chip owners.
- Lead signoff activities across STA, IR/EM, physical verification, logic equivalence checking, and low-power verification.
- Participate in RTL modifications and design reviews to support design convergence.
Requisitos
- Bachelor’s or master’s degree in Computer Engineering or Electrical Engineering.
- At least 8 years of experience in physical design.
- Experience with Tcl, Python, Perl, or tcsh scripting.
- Strong communication and collaboration skills.
- Customer-oriented, hands-on approach and ability to execute independently.
Se valora
- Experience with high-speed interfaces such as DDR or PCIe.
- Experience with advanced process nodes at 5nm or below.
- Experience building or maintaining implementation tools and flows.