Senior Physical Design Engineer
Join a networking silicon engineering team to implement and optimize physical designs for high-speed communication chips.
Responsabilidades
- Design complex physical-design units and ensure their integration into builds
- Run, debug, and approve place-and-route and verification flows across projects
- Implement, plan, and optimize physical designs for silicon chips
Requisitos
- Bachelor’s or master’s degree in Electrical Engineering
- At least 5 years of hands-on physical design place-and-route experience
- Experience with physical design methodology, including synthesis, floorplanning, clock-tree synthesis, and routing
- Experience with sign-off stages such as STA, physical verification, LEC, and EMIR
- Knowledge of advanced silicon process technologies
- Familiarity with physical-design EDA tools from Synopsys and Cadence
- Interest in using or learning AI tools
Se valora
- AI prompting experience
- Linux experience
- TCL, Python, or shell scripting
- Data collection and analysis experience
- Understanding of chip and die verification