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Senior PCIe Post-Silicon Validation Engineer
PresencialTiempo completoHardware EngineeringSemiconductors
Join a semiconductor connectivity company developing rack-scale infrastructure and validate PCIe silicon across platforms, configurations, generations, and operating conditions. The role focuses on hands-on link bring-up, physical-layer debugging, cross-functional issue resolution, and validation-—?
Responsabilidades
- Perform hands-on PCIe post-silicon validation.
- Debug link training, LTSSM, equalization, recovery, reset, and link-stability issues.
- Analyze protocol traces, registers, logs, eye diagrams, and laboratory measurements.
- Drive complex failures from initial detection through root-cause analysis and resolution.
- Collaborate with silicon, firmware, software, architecture, and signal-integrity engineers.
- Validate PCIe functionality across generations, platforms, configurations, and operating conditions.
- Create and execute validation plans, stress tests, corner-case scenarios, and interoperability tests.
- Develop automation for validation coverage, debugging efficiency, and regression testing.
Requisitos
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- At least 5 years of experience in silicon validation, post-silicon debugging, or high-speed interface development.
- Strong knowledge of PCIe architecture and protocol.
- Experience using PCIe analyzers, state-machine traces, registers, logs, eye diagrams, or signal-integrity measurements.
- Programming or scripting skills, preferably Python.
- Good Linux knowledge and experience with Linux PCIe debugging tools.
- Ability to independently investigate issues through root-cause analysis.
- Experience working across hardware, firmware, and software boundaries.
- Strong communication and collaboration skills.
Se valora
- Experience with PCIe Gen4, Gen5, Gen6, or Gen7.
- Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
- Experience with PCIe compliance, interoperability testing, and intermittent or corner-case failure analysis.
- Experience with PCIe switches, networking platforms, or accelerator platforms.
- Practical use of AI or machine-learning tools for engineering debugging and automation.