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Senior DFT Engineer

Astera Labs·Israel·
PresencialTiempo completoHardware EngineeringElectronics Manufacturing

Join a new Israeli R&D center developing advanced semiconductor connectivity chips for large-scale AI infrastructure. Own DFT methodology and silicon testability across the product lifecycle, from architecture through post-silicon bring-up and production.

Responsabilidades

  • Define DFT architectures and strategies for advanced connectivity chips.
  • Support DFT work across architecture, RTL design, backend implementation, production, and post-silicon support.
  • Design and implement JTAG/iJTAG, MBIST, Scan, and ATPG architectures.
  • Generate and optimize production test and debug patterns.
  • Perform STA for DFT modes and gate-level simulations.
  • Drive test coverage and quality metrics for manufacturing requirements.
  • Collaborate with architecture, verification, and backend engineering teams.
  • Develop and maintain DFT implementation flows.
  • Automate and improve DFT methodologies using scripting and engineering tools.

Requisitos

  • Bachelor’s degree in Electrical Engineering or a related technical field.
  • At least 4 years of hands-on DFT experience in semiconductor companies.
  • Experience with JTAG/iJTAG, MBIST, Scan, and ATPG DFT flows and architectures.
  • Understanding of logic design, verification, debugging, and Static Timing Analysis.
  • Proficiency in Tcl, Perl, Python, or Shell scripting.

Se valora

  • Master’s degree in Electrical Engineering or a related field.
  • Experience with Synopsys TestMAX or Siemens Tessent.
  • Experience with chip bring-up and mass-production activities.
  • Experience with advanced process technologies at 7nm and below.
  • Knowledge of PCIe, Ethernet, CXL, or UALink test requirements.
  • Experience working effectively in global engineering teams.

Compatibilidad

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Senior DFT Engineer for Advanced AI Connectivity Chips | CVZilla