Q
Senior Design Verification Engineer
PresencialTiempo completoHardware EngineeringSemiconductor Manufacturing
Verify peripheral IP and subsystems integrated into complex SoCs. The role is based on-site five days a week in Haifa, with options to work from Hod Hasharon or Ramat Gan.
Responsabilidades
- Verify IP- and subsystem-level peripherals integrated into complex SoCs.
- Own end-to-end verification, including testbench architecture, test planning, execution, and coverage closure.
- Develop and maintain UVM/SystemVerilog verification environments using constrained-random testing, assertions, and coverage-driven methods.
- Collaborate with design, architecture, software, and validation teams across multiple sites.
- Serve as a technical focal point for verification methodology, debugging, and quality.
Requisitos
- BSc or MSc in Electrical Engineering, Computer Engineering, or a related field.
- At least 5 years of hands-on design verification experience using SystemVerilog and UVM.
- Strong understanding of digital design fundamentals and SoC/IP-level architectures.
- Proficiency in UVM testbench architecture, including agents, sequences, scoreboards, and coverage models.
- Experience with constrained-random and coverage-driven verification, and debugging complex issues in large regression environments.
- Scripting and automation skills using Python, Perl, Tcl, or shell in a Linux/UNIX environment.
Se valora
- Experience with high-speed peripheral IP such as USB, PCIe, Display, SerDes, or similar I/O subsystems.
- Knowledge of low-power design, reset sequencing, and clock-domain interactions.
- Familiarity with regression management, verification metrics, and sign-off criteria.
- Experience collaborating with global, cross-site teams.
- Interest and potential to grow into a technical or team-lead role.
Beneficios
- Opportunity to work on peripheral IP used in high-volume products.
- Technical environment with opportunities to lead, influence, and mentor.
- Growth path toward technical leadership or people management.