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Senior Design-for-Test Engineer (ATPG)
Sin especificarTiempo completoHardware EngineeringSemiconductors
Experienced Design-for-Test Engineer to own ATPG flows end-to-end, from architecture and planning to pattern generation, verification, and post-silicon bring-up. Develop and maintain automation for short test times. Requires 5+ years DFT/ATPG experience, scripting, and BSc in EE/CE.
Responsabilidades
- Own state-of-the-art DFT/ATPG flows and implementation
- Take full ATPG ownership from architecture and planning through pattern generation, verification, and post-silicon bring-up and diagnosis
- Develop and maintain automation flows to minimize test time for production
Requisitos
- 5+ years of hands-on DFT/ATPG experience with ASIC design and ATPG tools
- Strong scripting skills (e.g., Python, TCL, Perl)
- BSc in Electrical Engineering or Computer Engineering
- Self-motivated, proactive, with a sense of ownership and commitment
Se valora
- Knowledge of scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
- Experience with Mentor TestKompress ATPG tool and retargeting flow
- Proficiency in TCL, Perl, Python, and Unix shell scripting
- Experience with ATE and silicon bring-up