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Senior Analog Layout Design Engineer
Sin especificarTiempo completoHardware EngineeringComputer Hardware Manufacturing
Join an advanced semiconductor design team to create and verify analog and mixed-signal physical layouts for high-speed ASIC functions in submicron CMOS technologies.
Responsabilidades
- Perform physical layout for PLLs, high-speed I/O circuits, SerDes, general I/O, and ESD structures
- Use Cadence tools for layout in advanced submicron CMOS FinFET technologies
- Collaborate with ASIC and mixed-signal engineers on design integration
- Handle floor planning, custom layout, and verification against design rules and schematics
- Perform EM/IR analysis
Requisitos
- At least 8 years of analog mask layout experience
- Electronics Practical Engineer certificate or B.Sc. in Electrical Engineering
- Understanding of analog layout concepts in submicron CMOS technologies, including operational amplifiers and ADCs/DACs
- Expertise with Cadence custom circuit design tools, especially Virtuoso
- Experience running and debugging DRC and LVS using tools such as ICV or Calibre
- Strong teamwork and interpersonal skills
Se valora
- Python or other scripting experience
- Knowledge of DRC and LVS checking flows
- Experience with EM/IR tools
- Ability to customize DRC and LVS decks