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Principal DFT Engineer
PresencialTiempo completoHardware EngineeringSemiconductor Manufacturing
Lead design-for-test strategy and execution for complex semiconductor chips powering high-performance AI connectivity systems. Own DFT work from architecture and specification through implementation, verification, tapeout, silicon bring-up, and production support.
Responsabilidades
- Define DFT architecture for complex SoCs, including scan, memory BIST, logic BIST, JTAG or iJTAG, and ATPG strategies.
- Lead DFT planning, specification, quality tracking, and sign-off readiness through tapeout.
- Direct DFT implementation, integration, and verification at block, full-chip, and chiplet levels.
- Own DFT activities from specification through silicon bring-up and production support.
- Drive test coverage, pattern generation, and alignment with manufacturing requirements.
- Develop scalable DFT methodologies, flows, and automation frameworks.
- Collaborate with RTL, physical design, STA, and test engineering teams on DFT readiness.
- Optimize front-end and backend DFT integration to improve quality, PPA, and turnaround time.
Requisitos
- Bachelor’s degree in Electrical Engineering or a related technical field; a master’s degree is preferred.
- At least 12 years of experience in DFT design, implementation, and verification for complex ASIC or SoC designs.
- Demonstrated leadership of DFT activities across complete chip development cycles.
- Deep expertise in Scan, MBIST, LBIST, JTAG or iJTAG, and ATPG.
- Strong understanding of DFT and physical design flows, timing implications, and integration challenges.
- Experience with Siemens Tessent, Synopsys TestMAX, or equivalent DFT tools.
- Experience with DFT verification methodologies and coverage analysis.
- Strong Tcl, Python, or Perl scripting skills for automation and flow development.
Se valora
- Experience with advanced process nodes of 7nm or below.
- Background in high-speed connectivity designs such as PCIe, Ethernet, or CXL.
- Experience with hierarchical DFT and large multi-die or chiplet-based systems.
- Knowledge of silicon bring-up, production test flows, and yield optimization.
- Familiarity with STA, low-power design, and CDC as they relate to DFT integration.