Physical Design Manager
Lead a team of engineers responsible for backend methodology and physical design flows from RTL to GDS for complex ASICs and VLSI devices.
Responsabilidades
- Provide strategic and technical leadership to the physical design engineering team
- Own team output across definition, physical synthesis, place and route, optimization, timing closure, and design floor planning
- Guide engineers through the complete chip design lifecycle
- Develop and improve backend methodology and RTL-to-GDS flows
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering
- At least 10 years of hands-on experience in VLSI backend or a relevant physical design domain
- At least 4 years of management or technical leadership experience
- Strong understanding of place-and-route flows
Se valora
- Deep knowledge of physical construction and integration
- Knowledge of LVS/DRC physical design verification methodologies
- Familiarity with Synopsys, Cadence, or comparable physical design EDA tools