Physical Design Engineer
Responsible for physical design of networking silicon, including RTL-to-GDS flow, synthesis, place and route, timing closure, power/noise analysis, and physical verification. Requires strong knowledge of PNR, STA, and EDA tools.
Responsabilidades
- Physical design of blocks according to specifications under challenging constraints targeting best power, area, and performance.
- Work on challenging designs including high cell count and high-speed blocks, resolving complex timing and congestion problems.
- Perform all aspects of physical design chip development (RTL2GDS): synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
- Take part in flows development.
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or equivalent work experience.
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
- Deep understanding of all aspects of physical construction and integration.
- Knowledge in physical design verification methodology LVS/DRC.
- Familiarity with physical design EDA tools such as Synopsys, Cadence.
- Great teammate.