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Mid-Level STA Physical Design Engineer
PresencialTiempo completoHardware EngineeringSemiconductors
Work on static timing analysis and DFT physical design for high-speed networking chips, supporting constraints, timing closure, flow development, and sign-off.
Responsabilidades
- Execute DFT static timing analysis from RTL-driven constraints and definitions through constraint quality assurance and STA sign-off
- Generate constraints, environments, and timing models for block-level and full-chip designs
- Generate timing ECOs
- Contribute to pre-silicon and post-silicon analysis of DFT designs
- Develop and improve timing analysis flows
Requisitos
- Bachelor's degree in Electrical Engineering or Computer Engineering
- 2–3 years of experience as an STA engineer
- Ability to adapt quickly to new technologies and develop expertise in new areas
- Strong communication skills
- Collaborative approach and ability to work effectively in a team
- Ability to develop solutions in response to technical issues
Se valora
- Knowledge of physical design flows, including place-and-route, STA, and physical verification
- Knowledge of DFT flows such as ATPG, MBIST, and IJTAG
- Experience with DFT timing closure
- Knowledge of clock-domain crossing (CDC)
- Familiarity with Synopsys, Cadence, or similar physical design EDA tools