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Junior VLSI Verification Engineer
Sin especificarTiempo completoHardware EngineeringElectronics Manufacturing
Join an electronics technology team to verify digital designs and IP blocks using SystemVerilog and UVM. Develop testbenches, debug simulations, analyze coverage, and collaborate with design engineers through verification sign-off.
Responsabilidades
- Develop, debug, and maintain SystemVerilog and UVM verification environments and testbenches
- Analyze simulation results and waveforms to isolate and root-cause design or testbench bugs
- Define, track, and analyze code and functional coverage metrics
- Drive coverage closure for assigned design blocks
- Own verification of assigned IP blocks or features from test planning through sign-off
- Collaborate with design engineers to clarify specifications and confirm verification completeness
- Escalate complex issues and incorporate feedback from senior engineers
- Participate in code reviews and technical knowledge-sharing sessions
Requisitos
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- 1–2 years of VLSI verification experience
- Working knowledge of SystemVerilog and UVM fundamentals
- Basic understanding of digital design and verification concepts, including RTL structure, testbench architecture, and simulation flow
- Strong problem-solving skills and willingness to learn new tools and methodologies
- Detail-oriented approach and effective communication skills
Se valora
- Basic Python skills for scripting and test automation
- Familiarity with Git or other version control systems
- Experience with VCS, Xcelium, or Questa
- Understanding of code and functional coverage
- Familiarity with AXI, APB, I2C, or SPI protocols
Beneficios
- Collaborative and supportive work environment
- International project collaboration
- Work on products used in critical electronics systems
- Opportunities for learning and professional growth
- Access to modern machine learning, platforms, and engineering tools