C
ASIC Engineer
Sin especificarTiempo completoHardware EngineeringNetworkingSemiconductors
Responsible for micro-architecture review, UVM-based verification environment implementation, and post-silicon validation of high-scale networking silicon.
Responsabilidades
- Review micro-architecture specifications
- Implement UVM-based verification environments
- Collaborate with design engineers to resolve bugs and achieve coverage closure
- Verify chip flows with firmware and lab teams
- Perform debug, root-cause analysis, and post-silicon validation in the lab
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering
- 4+ years of experience in chip design or verification
- Knowledge of UVM and functional verification methodologies
Se valora
- Experience with MATLAB simulations and bit-exact modeling
- Familiarity with mixed-signal systems
- Hands-on experience with Clock Domain Crossing (CDC)